Group III-V Device Including a Shield Plate

ABSTRACT

There are disclosed herein various implementations of a group III-V device including a shield plate. Such a group III-V device includes a substrate, a transition body situated over the substrate, a device channel layer situated over the transition body, and a device barrier layer situated over the device channel layer and producing a device two-dimensional electron gas (2-DEG). The group III-V device also includes a drain electrode coupled to the device barrier layer, and a shield plate, which may be coupled to the drain electrode or may be a floating shield plate. The shield plate is configured to substantially shield the device 2-DEG from charge centers situated over the device barrier layer.

The present application claims the benefit of and priority to aprovisional application entitled “Shielded 2-DEG HEMTs,” Ser. No.62/001,200 filed on May 21, 2014. The disclosure in this provisionalapplication is hereby incorporated fully by reference into the presentapplication.

BACKGROUND I. Definition

As used herein, the phrase “group III-V” refers to a compoundsemiconductor including at least one group III element and at least onegroup V element. By way of to example, a group III-V semiconductor maytake the form of a III-Nitride semiconductor. “III-Nitride” or “III-N”refers to a compound semiconductor that includes nitrogen and at leastone group III element such as aluminum (Al), gallium (Ga), indium (In),and boron (B), and including but not limited to any of its alloys, suchas aluminum gallium nitride (Al_(x)Ga_((1-x))N), indium gallium nitride(In_(y)Ga_((1-y))N), aluminum indium gallium nitride(AlIn_(y)Ga_((1-x-y))N), gallium arsenide phosphide nitride(GaAs_(a)P_(b)N_((1-a-b))), aluminum indium gallium arsenide phosphidenitride (Al_(x)In_(y)Ga_((1-x-y))As_(a)P_(b)N_((1-a-b)) for example.III-N also refers generally to any polarity including but not limited toGa-polar, N-polar, semi-polar, or non-polar crystal orientations. AIII-N material may also include either the Wurtzitic, Zincblende, ormixed polytypes, and may include single-crystal, monocrystalline,polycrystalline, or amorphous structures. Gallium nitride or GaN, asused herein, refers to a III-N compound semiconductor wherein the groupIII element or elements include some or a substantial amount of gallium,but may also include other group III elements in addition to gallium.

In addition, as used herein, the phrase “group IV” refers to asemiconductor that includes at least one group IV element such assilicon (Si), germanium (Ge), and carbon (C), and may also includecompound semiconductors such as silicon germanium (SiGe) and siliconcarbide (SiC), for example. Group IV also refers to semiconductormaterials which include more than one layer of group IV elements, ordoping of group IV elements to produce strained group IV materials, andmay also include group IV based composite substrates such assingle-crystal or polycrystalline SiC on silicon, silicon on insulator(SOT), separation by implantation of oxygen (SIMOX) process substrates,and silicon on sapphire (SOS), for example.

It is noted that, as used herein, the terms “low voltage” or “LV” inreference to a transistor or switch describes a transistor or switchwith a voltage range of up to approximately fifty volts (50V). It isfurther noted that use of the term “midvoltage” or “MV” refers to avoltage range from approximately fifty volts to approximately twohundred volts (approximately 50V to 200V). Moreover, the term “highvoltage” or “HV,” as used herein, refers to a voltage range fromapproximately two hundred volts to approximately twelve hundred volts(approximately 200V to 1,200V), or higher.

II. Background Art

In high power and high performance circuit applications, group III-Vfield-effect transistors (FETs), such as gallium nitride (GaN) or otherIII-Nitride based high mobility electron transistors (HEMTs), are oftendesirable for their high efficiency and high-voltage operation.III-Nitride and other group III-V HEMTs operate using polarizationfields to generate a two-dimensional electron gas (2-DEG) allowing forhigh current densities with low resistive losses. Although their highbreakdown voltage, high current density, and very low specificon-resistance render group III-V HEMTs potentially advantageous for usein power applications, III-Nitride and other group III-V HEMTs aresusceptible to having their performance degraded due to charge trapping.

Charge trapping may result from the presence of charge centers residingin the various material layers used to fabricate the HEMT, as well as atinterfaces between those layers. For example, charge centers may befound in or at the interface of the capping, passivation, dielectric,and package material layers overlying the active channel and barrierlayers of the group III-V HEMT. Due to the insulating or semi-insulatingnature of the layers in which the charge centers may reside, the fieldsarising from those charge centers are typically not screened from thedevice 2-DEG and can undesirably increase the on-resistance of the HEMT.

SUMMARY

The present disclosure is directed to a group III-V device including ashield plate, substantially as shown in and/or described in connectionwith at least one of the figures, and as set forth in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of an exemplary group III-V deviceincluding a shield two-dimensional electron gas (2-DEG) configured toshield the device 2-DEG from charge centers situated in the devicestructure, according to one implementation.

FIG. 2 shows a cross-sectional view of an exemplary group III-V deviceincluding a shield layer configured to shield the device 2-DEG fromcharge centers situated in the device structure, according to oneimplementation.

FIG. 3A shows a cross-sectional view of an exemplary group III-V deviceincluding a shield plate configured to shield the device 2-DEG fromcharge centers situated in the device structure, according to oneimplementation.

FIG. 3B shows a cross-sectional view of an exemplary group III-V deviceincluding a shield plate configured to shield the device 2-DEG fromcharge centers situated in the device structure, according to anotherimplementation.

FIG. 4A shows a top view of an exemplary shield plate arrangementconfigured to shield the device 2-DEG of FIG. 3A and/or FIG. 3B fromcharge centers situated in the device structure, according to oneimplementation.

FIG. 4B shows a top view of an exemplary shield plate arrangementconfigured to shield the device 2-DEG of FIG. 3A and/or FIG. 3B fromcharge centers situated in the device structure, according to anotherimplementation.

FIG. 5 shows a cross-sectional view of an exemplary group III-V deviceincluding a shield plate configured to shield the device 2-DEG fromcharge centers situated in the device structure, according to anotherimplementation.

FIG. 6A shows a cross-sectional view of an exemplary group III-V deviceincluding a shield layer and a shield plate configured to shield thedevice 2-DEG from charge centers situated in the device structure,according to one implementation.

FIG. 6B shows a cross-sectional view of an exemplary group III-V deviceincluding a shield layer and a shield plate configured to shield thedevice 2-DEG from charge centers situated in the device structure,according to another implementation.

DETAILED DESCRIPTION

The following description contains specific information pertaining toimplementations in the present disclosure. One skilled in the art willrecognize that the present disclosure may be implemented in a mannerdifferent from that specifically discussed herein. The drawings in thepresent application and their accompanying detailed description aredirected to merely exemplary implementations. Unless noted otherwise,like or corresponding elements among the figures may be indicated bylike or corresponding reference numerals. Moreover, the drawings andillustrations in the present application are generally not to scale, andare not intended to correspond to actual relative dimensions.

As noted above, despite their many desirable performancecharacteristics, including high breakdown voltage, high current density,and very low specific on-resistance, III-Nitride and other group III-Vhigh electron mobility transistors (HEMTs) are susceptible to havingtheir performance degraded due to charge trapping. As further notedabove, charge trapping may result from the presence of charge centersresiding in the various material layers used to fabricate the HEMT, aswell as at interfaces between those layers. For example, charge centersmay be found in or at the interface of the device substrate, transitionlayers, and buffer layers underlying the active channel and barrierlayers of a group III-V HEMT, as well as in or at the interface of thecapping, passivation, dielectric, and package material layers overlyingthe active channel and barrier layers of the group III-V HEMT.

The causes of charge trapping are varied, and may include charge centersformed as point defects in the group III-V material (impurities,vacancies, interstitials, for example) or charge centers in the form ofdangling bonds at the various bulk, surface, and layer interfaces. Dueto the insulating or semi-insulating nature of the layers in which thecharge centers may reside, the fields arising from those charge centersare typically not screened from the device two-dimensional electron gas(2-DEG) and can degrade the transport properties of the high mobilityelectrons in the device 2-DEG. This can result in increased resistanceof the HEMT through reduction in the number of conduction electronsand/or reduction in the mobility of a population of the conductionelectrons.

FIG. 1 shows a cross-sectional view of exemplary group III-V device 100configured to provide shielding from charge centers situated under thedevice 2-DEG, according to one implementation. As shown in FIG. 1, groupIII-V device 100 includes substrate 110, transition body 122 situatedover substrate 110, and buffer layer 124 situated over transition body122. In addition, FIG. 1 shows device channel layer 142 situated overtransition body 122, and device barrier layer 144 situated over devicechannel layer 142 to produce device 2-DEG 146. Also shown in FIG. 1 areshield channel layer 132, shield barrier layer 134 situated over shieldchannel layer 132 to produce shield 2-DEG 136, and graded layer orlayers 126 situated between shield barrier layer 134 and device channellayer 142.

Moreover, and as further shown in FIG. 1, group III-V device 100includes drain electrode 102, source electrode 104, and gate electrode106, and may have charge centers 190 and/or 192 situated betweensubstrate 110 and device channel layer 142. Drain electrode 102 andsource electrode 104 are configured such that they make ohmic contactwith device 2-DEG 146. Gate electrode 106 may correspond to a Schottkygate configured to make Schottky contact with device barrier layer 144,or may correspond to an insulated gate configured to couple capacitivelyto device barrier layer 144. It is noted that group Ill-V device 100having the features shown in FIG. 1 may be implemented as a III-Nitrideor other group III-V HEMT or FET device or hybrid FET/HEMT device.

According to the implementation shown in FIG. 1, device 2-DEG 146 isproduced by device barrier layer 144 and device channel layer 142 overgraded layer(s) 126, shield barrier layer 134, and shield channel layer132. As a result, shield 2-DEG 136 produced by shield barrier layer 134and shield channel layer 132 is situated so as to substantially shielddevice 2-DEG 146 from charge trapping resulting from the presence ofcharge centers 190 and 192 below shield 2-DEG 136. That is to say,shield 2-DEG 136 is configured to substantially shield device 2-DEG 146from charge centers 190 and 192 situated between substrate 110 andshield 2-DEG 136.

Substrate 110 may be formed of any commonly utilized substrate material.For example, substrate 110 may be formed of sapphire, may be a nativegroup III-V substrate, or may be a group IV substrate as described abovein the “Definitions” section. Transition body 122 may be formed ofmultiple III-Nitride or other group III-V layers situated over substrate110. In some implementations, transition body 122 may take the form of agroup III-V body including compositionally graded layers and havingdifferent group III-V alloy compositions at respective top and bottomsurfaces.

Examples of using compositionally graded transition layers, as well asuse of intermediate layers, stress reducing layers, and variousinterlayers are disclosed in U.S. Pat. No. 6,649,287, entitled “GalliumNitride Materials and Methods”, filed on Dec. 14, 2000, and issued onNov. 18, 2003; U.S. Pat. No. 6,617,060, also entitled “Gallium NitrideMaterials and Methods”, filed on Jul. 2, 2002, and issued on Sep. 9,2003; U.S. Pat. No. 7,339,205, entitled “Gallium Nitride Materials andMethods Associated with the Same”, filed on Jun. 28, 2004, and issued onMar. 4, 2008; U.S. Pat. No. 8,344,417, entitled “Gallium NitrideSemiconductor Structures with Compositionally-Graded Transition Layer”,filed on Jan. 27, 2012, and issued on Jan. 1, 2013; U.S. Pat. No.8,592,862, also entitled “Gallium Nitride Semiconductor Structures withCompositionally-Graded Transition Layer”, filed on Dec. 27, 2012, andissued on Nov. 26, 2013; U.S. Pat. No. 8,957,454, entitled “III-NitrideSemiconductor Structures with Strain Absorbing Interlayer TransitionModules”, filed on Feb. 24, 2012 and issued on Feb. 17, 2015; U.S.patent application Ser. No. 12/928,946, entitled “Stress Modulated GroupIII-V Semiconductor Device and Related Method”, filed on Dec. 21, 2010,and published as U.S. Patent Application Publication Number 2012/0153351on Jun. 21, 2012; and U.S. patent application Ser. No. 11/531,508,entitled “Process for Manufacture of Super Lattice Using AlternatingHigh and Low Temperature Layers to Block Parasitic Current Path”, filedon Sep. 13, 2006, and published as U.S. Patent Application PublicationNumber 2007/0056506 on Mar. 15, 2007. The disclosures in theabove-referenced patents and patent applications are hereby incorporatedfully by reference into the present application.

Although not shown in FIG. 1, in some implementations, group III-Vdevice 100 may also include a strain-absorbing layer formed betweensubstrate 110 and transition body 122. Such a strain-absorbing layer maybe an amorphous strain-absorbing layer, for example, an amorphoussilicon nitride layer. It is noted that in implementations in whichsubstrate 110 is a non-native substrate for device channel layer 142 anddevice barrier layer 144 (i.e., a non group III-V substrate, such as asilicon or other group IV substrate), transition body 122 is provided tomediate the lattice transition from substrate 110 to buffer layer 124.

In one implementation, transition body 122 may include a nucleationlayer (nucleation layer not shown in FIG. 1), in addition to layersformed so as to reduce the net mismatch in thermal coefficient ofexpansion between substrate 110 and later formed group III-V activelayers, such as device channel layer 142 and device barrier layer 144.For instance, when forming a gallium nitride (GaN) based group III-Vdevice, transition body 122 may include an aluminum nitride (AlN) layerformed on substrate 110, or on a strain-absorbing layer and/or anucleation layer formed on substrate 110, and may further include aseries of intermediate layers, such as aluminum gallium nitride (AlGaN)layers having a progressively reduced aluminum content relative to theirgallium content, until a suitable transition to a GaN buffer implementedas buffer layer 124 is achieved.

As noted above, in some implementations, transition body 122 may includecompositionally graded III-Nitride or other group III-V materials. Insuch implementations, the specific compositions and thicknesses of thelayers included in transition body 122 may depend on the diameter andthickness of substrate 110, and the desired performance of group III-Vdevice 100. For example, the desired breakdown voltage of group III-Vdevice 100, as well as the desired bow and warp of the associatedepitaxial wafer supporting fabrication of group III-V device 100 caninfluence the compositions and thicknesses of the layers used to formtransition body 122, as known in the art.

Buffer layer 124 is situated over transition body 122 and may be aIII-Nitride or other group III-V material layer formed using any of anumber of known growth techniques. For example, in implementations inwhich group III-V device 100 is a GaN based HEMT, buffer layer 124 maybe a compositionally graded GaN based layer. Moreover, in someimplementations, buffer layer 124 may take the form of a III-Nitride orother group III-V layer including a group III material having analuminum concentration in a range from approximately four percent toapproximately eight percent, for example an AlGaN layer having such analuminum concentration. Buffer layer 124 may be formed using anysuitable technique for forming III-Nitride or other group III-V basedlayers, such as molecular-beam epitaxy (MBE), metalorganic chemicalvapor deposition (MOCVD), or hydride vapor phase epitaxy (HVPE), to namea few suitable approaches. It is noted that any of MBE, MOCVD, or HVPE,for example, may also be used to form transition body 122.

As shown in FIG. 1, formation of transition body 122 and buffer layer124 over substrate 110 can result in the inadvertent formation of chargecenters 190 and/or 192. Charge centers 190 and/or 192 may be formed aspoint defects, such as impurities, vacancies, and interstitials, forexample, in the group III-V materials used to provide transition body122 and buffer layer 124. Alternatively, or in addition, charge centers190 and/or 192 may be present in the form of dangling bonds or othercharge trapping sites situated at an interface between substrate 110 andtransition body 122, and/or at an interface between transition body 122and buffer layer 124.

As further shown in FIG. 1, shield channel layer 132 is formed overbuffer layer 124, and shield barrier layer 134 is formed over shieldchannel layer 132 to produce shield 2-DEG 136 configured tosubstantially shield device 2-DEG 146 from charge centers 190 and 192.Shield channel layer 132 and shield barrier layer 134 may be formed ofany group III-V materials suitable for producing shield 2-DEG 136. Forexample, shield channel layer 132 may be formed as a GaN or indiumgallium nitride (InGaN) layer. Shield barrier layer 134 may be formed asa group III-V layer having a larger bandgap than shield channel layer132, and may take the form of an AlN layer, or an AlGaN layer, forexample. Shield channel layer 132 and shield barrier layer 134 may beformed using any of MBE, MOCVD, or HVPE.

Although shield 2-DEG 136 may be a desirable feature of group III-Vdevice 100 for substantially shielding device 2-DEG 146 from chargecenters 190 and 192, it is typically undesirable for shield 2-DEG 136 tocontribute to the conduction of group III-V device 100. For example,unless suitably isolated from device 2-DEG 146, shield 2-DEG 136 mayadversely affect the pinch-off voltage, off-state leakage, breakdown, orotherwise impact the performance or reliability of group III-V device100. As a result, it may be advantageous or desirable to ensure thatneither drain electrode 102 nor source electrode 104 makes ohmic contactwith shield 2-DEG 136, and to electrically isolate device 2-DEG 146 fromshield 2-DEG 136. According to the implementation shown in FIG. 1, suchelectrical isolation of device 2-DEG 146 from shield 2-DEG 136 isprovided by graded layer(s) 126.

Graded layer(s) 126 may be formed as a single compositionally gradedgroup III-V layer, or as a stack of group III-V layers having differentgroup III-V compositions. Graded layer(s) 126 may be in the range ofapproximately 0.1 to 2.0 micrometer thick. The compositional gradingscheme of graded layer(s) 126 may be continuous or stepped, for example.In some implementations, graded layer(s) 126 may take the form of acompositionally graded III-Nitride or other group III-V layer, or acompositionally graded stack of group III-V layers, including a groupIII material having an aluminum concentration in a range fromapproximately four percent to approximately eight percent, for examplean AlGaN layer or stack having such an aluminum concentration.

Moreover, in some implementations, it may be advantageous or desirableto form graded layer(s) 126 using an impurity graded scheme as disclosedin U.S. Pat. No. 8,796,738, entitled “Group III-V Device StructureHaving a Selectively Reduced Impurity Concentration”, filed on Sep. 5,2012, and issued on Aug. 5, 2014. This patent is hereby incorporatedfully by reference into the present application. Graded layer(s) 126 maybe formed using any of MBE, MOCVD, or HVPE.

Device channel layer 142 is formed over graded layer(s) 126, and devicebarrier layer 144 is formed over device channel layer 142 using any ofMBE, MOCVD, or HVPE, for example. In addition a thin group III-V cappinglayer may be used over device barrier layer 144 (capping layer not shownin FIG. 1). In one implementation, for example, group III-V device 100may take the form of a III-Nitride HEMT having a GaN layer as devicechannel layer 142 and an AlGaN layer as device barrier layer 144. It isnoted that, in some implementations, the optional capping layerdescribed above may be formed of GaN or AlGaN and may be intentionallydoped or may be substantially undoped. However, in otherimplementations, the optional capping layer may be formed of aninsulating material. such as silicon nitride (Si₃N₄), for example.

It is further noted that in some implementations, it may be advantageousor desirable to form device barrier layer 144 over a spacer layer (orlayers) disposed between device barrier layer 144 and device channellayer 142 (spacer layer or layers also not shown in FIG. 1). Examples ofusing such spacer layer(s) are disclosed in U.S. Pat. No. 8,659,030,entitled “III-Nitride Heterojunction Devices Having a MultilayerSpacer”, filed on Feb. 15, 2012, and issued on Feb. 25, 2014. Thispatent is hereby incorporated fully by reference into the presentapplication. It is also noted that the discussion above regardingsubstrate 110, transition body 122, buffer layer 124, device channellayer 142, and device barrier layer 144 applies respectively to thesubstrates, transition bodies, buffer layers, device channel layers, anddevice barrier layers in various other implementations of the presentdisclosure, such as those discussed in relation to FIGS. 2, 3A, 3B, 5,6A, and 6B below.

Thus, as disclosed in the present application, the degradation inperformance seen in group III-V devices such as III-Nitride HEMTs due tocharge trapping in conventional device structures is reduced orsubstantially eliminated due to a shielding element formed below thedevice 2-DEG. According to the exemplary implementation shown in FIG. 1,for example, shield 2-DEG 136 produced by shield barrier layer 134 andshield channel layer 132 substantially shields device 2-DEG 146 fromcharge centers 190 and 192 situated between substrate 110 and shield2-DEG 136.

Referring to FIG. 2, FIG. 2 shows a cross-sectional view of exemplarygroup III-V device 200 including a shield layer configured to shield thedevice 2-DEG from charge centers situated in the device structure,according to one implementation. As shown in FIG. 2, group III-V device200 includes substrate 210, transition body 222 situated over substrate210, and first buffer layer 224 situated over transition body 222. Inaddition, FIG. 2 shows device channel layer 242 situated over transitionbody 222, and device barrier layer 244 situated over device channellayer 242 to produce device 2-DEG 246. Also shown in FIG. 2 are shieldlayer 230, and second buffer layer 228 situated between shield layer 230and device channel layer 242. Moreover, and as further shown in FIG. 2,group III-V device 200 includes drain electrode 202, source electrode204, and gate electrode 206, and may have charge centers 290 and/or 292situated between substrate 210 and device channel layer 242.

Substrate 210, transition body 222, first buffer layer 224, and chargecenters 290 and 292 correspond in general to substrate 110, transitionbody 122, buffer layer 124, and charge centers 190 and 192,respectively, in FIG. 1, and may share any of the characteristicsattributed to those corresponding features, above. In addition, devicechannel layer 242, device barrier layer 244, and device 2-DEG 246, inFIG. 2, correspond in general to device channel layer 142, devicebarrier layer 144, and device 2-DEG 146, respectively, in FIG. 1, andmay analogously share any of the characteristics attributed to thosecorresponding features, above. Moreover, drain electrode 202, sourceelectrode 204, and gate electrode 206, in FIG. 2, correspond in generalto drain electrode 102, source electrode 104, and gate electrode 106,respectively, in FIG. 1, and may share any of the characteristicsattributed to those corresponding features, above.

Group III-V device 200 having the features shown in FIG. 2 may beimplemented as a III-Nitride or other group III-V HEMT or FET device orhybrid FET/HEMT device. Moreover, it is noted that in addition to thefeatures shown in FIG. 2, group III-V device 200 may further includesome or all of the strain-absorbing, spacer, and capping layersdescribed above by reference to FIG. 1. For example, group III-V device200 may include an amorphous silicon nitride strain-absorbing layerbetween substrate 210 and transition body 222, and/or one or more spacerlayers between device channel layer 242 and device barrier layer 244,and/or a group III-V or insulating capping layer over device barrierlayer 244, as discussed above.

According to the implementation shown in FIG. 2, device 2-DEG 246 isproduced by device barrier layer 244 and device channel layer 242 oversecond buffer layer 228 and shield layer 230. As a result, shield layer230 is situated so as to substantially shield device 2-DEG 246 fromcharge trapping resulting from the presence of charge centers 290 and292 below shield layer 230. That is to say, shield layer 230 isconfigured to substantially shield device 2-DEG 246 from charge centers290 and 292 situated between substrate 210 and shield layer 230.

First buffer layer 224 is situated over transition body 222 and may be aIII-Nitride or other group III-V material layer formed using any of MBE,MOCVD, or HVPE, for example. For instance, in implementations in whichgroup III-V device 200 is a GaN based HEMT, first buffer layer 224 maybe a compositionally graded GaN based layer, as described above.Moreover, in some implementations, first buffer layer 224 may take theform of a III-Nitride or other group III-V layer including a group IIImaterial having an aluminum concentration in a range from approximatelyfour percent to approximately twenty percent, for example an AlGaN layerhaving such an aluminum concentration.

As shown in FIG. 2, shield layer 230 is formed over first buffer layer224. Shield layer 230 may be an N doped or P doped III-Nitride or othergroup III-V layer. In implementations in which shield layer 230 is an Ndoped layer, shield layer 230 may be formed as a thin GaN or AlGaN layerdoped with silicon or germanium, for example. In order to effectivelyshield device 2-DEG 246 from charge centers 290 and/or 292, the dopingconcentration of shield layer 230 should be on the order of the carrierconcentration of device 2-DEG 246, e.g., approximately 10¹³ charge/cm².As a result, shield layer 230 will typically have a doping concentrationof at least approximately 10¹² charge/cm². Shield layer 230 may beformed using any of MBE, MOCVD, or HVPE, for example.

It is noted that although FIG. 2 shows shield layer 230 to be situatedover first buffer layer 224, in some implementations it may beadvantageous or desirable to situate shield layer 230 below first bufferlayer 224. For example, in some implementations, shield layer 230 may besituated in transition body 220, amongst the transition layers formingtransition body 220.

It is further noted that although shield layer 230 may be a desirablefeature of group III-V device 200 for substantially shielding device2-DEG 246 from charge centers 290 and 292, it is typically undesirablefor shield layer 230 to contribute to the conduction of group III-Vdevice 200. For example, unless suitably isolated from device 2-DEG 246,shield layer 230 may adversely affect the pinch-off voltage, off-stateleakage, breakdown, or otherwise impact the performance or reliabilityof group III-V device 200. As a result, it may be advantageous ordesirable to ensure that neither drain electrode 202 nor sourceelectrode 204 makes ohmic contact with shield layer 230, and toelectrically isolate device 2-DEG 246 from shield layer 230. Accordingto the implementation shown in FIG. 2, such electrical isolation ofdevice 2-DEG 246 from shield layer 230 is provided by second bufferlayer 228.

Second buffer layer 228 may be a III-Nitride or other group III-Vmaterial layer formed using any of MBE, MOCVD, or HVPE, for example. Forinstance, in implementations in which group III-V device 200 is a GaNbased HEMT, second buffer layer 228 may be a compositionally graded GaNbased layer, as described above. Moreover, in some implementations,second buffer layer 228 may take the form of a III-Nitride or othergroup III-V layer including a group III material having an aluminumconcentration in a range from approximately four percent toapproximately twelve percent, for example an AlGaN layer having such analuminum concentration.

Thus, according to the exemplary implementation shown in FIG. 2, shieldlayer 230 is configured to substantially shield device 2-DEG 246 fromcharge centers 290 and 292 situated between substrate 210 and shieldlayer 230. As a result, the degradation in group III-V deviceperformance due to charge trapping in conventional device structures isreduced or substantially eliminated in group III-V device 200 due to thepresence of shield layer 230 below device 2-DEG 246.

Although the implementations shown in FIG. 1 and FIG. 2 address chargetrapping due to charge centers situated below a device 2-DEG, as notedabove, charge trapping may also occur due to the presence of chargecenters above the device 2-DEG. For example, charge centers may be foundin the various material layers formed over the device 2-DEG, such ascapping, passivation, field dielectric, and inter-layer dielectric (ILD)layers, as well as at the interfaces of those layers. In addition,charge trapping may occur due to charge centers in the packagingmaterial used to house the group III-V device. FIGS. 3A, 3B, 4A, 4B, 5,6A, and 6B show exemplary implementations of group III-V devicesconfigured to provide shielding from charge centers situated above thedevice 2-DEG.

Referring to FIG. 3A, FIG. 3A shows a cross-sectional view of exemplarygroup III-V device 300A including a shield plate configured to shielddevice 2-DEG 346 from charge centers 394 and 396 above shield plate 360a and field plate 316, according to one implementation. As shown in FIG.3A, group III-V device 300A includes substrate 310, transition body 322situated over substrate 310, and buffer layer 324 situated overtransition body 322. In addition, FIG. 3A shows device channel layer 342situated over transition body 322, and device barrier layer 344 situatedover device channel layer 342 to produce device 2-DEG 346. Also shown inFIG. 3A are dielectric layer 350, passivation layer 370, and packagematerial 380, all situated above device barrier layer 344. Moreover, andas further shown in FIG. 3A, group III-V device 300A includes drainelectrode 302, source electrode 304, gate electrode 306, field plate 316overlying gate electrode 306, and shield plate 360 a coupled to drainelectrode 302. In addition, FIG. 3A shows separation thickness 352 ofdielectric layer 350 spacing shield plate 360 a apart from field plate316.

Substrate 310, transition body 322, and buffer layer 324 correspond ingeneral to substrate 110, transition body 122, and buffer layer 124,respectively, in FIG. 1, and may share any of the characteristicsattributed to those corresponding features, above. In addition, devicechannel layer 342, device barrier layer 344, and device 2-DEG 346, inFIG. 3A, correspond in general to device channel layer 142, devicebarrier layer 144, and device 2-DEG 146, respectively, in FIG. 1, andmay analogously share any of the characteristics attributed to thosecorresponding features, above. Moreover, drain electrode 302, sourceelectrode 304, and gate electrode 306, in FIG. 3A, correspond in generalto drain electrode 102, source electrode 104, and gate electrode 106,respectively, in FIG. 1, and may share any of the characteristicsattributed to those corresponding features, above.

Group III-V device 300A having the features shown in FIG. 3A may beimplemented as a III-Nitride or other group III-V HEMT or FET device orhybrid FET/HEMT device. Moreover, it is noted that in addition to thefeatures shown in FIG. 3A, group III-V device 300A may further includesome or all of the strain-absorbing, spacer, and capping layersdescribed above by reference to FIG. 1. For example, group III-V device300A may include an amorphous silicon nitride strain-absorbing layerbetween substrate 310 and transition body 322, and/or one or more spacerlayers between device channel layer 342 and device barrier layer 344,and/or a group III-V or insulating capping layer over device barrierlayer 344, as discussed above.

According to the implementation shown in FIG. 3A, device 2-DEG 346 isproduced by device barrier layer 344 and device channel layer 342 and issituated under shield plate 360 a. As a result, shield plate 360 a issituated so as to substantially shield device 2-DEG 346 from chargetrapping resulting from the presence of charge centers 394 and 396 aboveshield plate 360 a.

Dielectric layer 350 and passivation layer 370 may be formed of anysuitable dielectric materials, and may be formed using any suitabletechnique known in the art. For example, passivation layer 370 may be aSi₃N₄, layer, while dielectric layer 350 may be implemented usingsilicon dioxide (SiO₂). Moreover, package material 380 may be anymaterial suitable for use as an encapsulant in semiconductor packaging.For example, package material 380 may be an epoxy resin based moldingcompound.

As shown in FIG. 3A, formation of dielectric layer 350, passivationlayer 370, and package material 380 over device barrier layer 344 canresult in the inadvertent formation of charge centers 394 and/or 396.Charge centers 394 and/or 396 may be formed as point defects, such asimpurities, vacancies, and interstitials, for example, in the materialsused to provide dielectric layer 350, passivation layer 370, and packagematerial 380. Alternatively, or in addition, charge centers 394 and/or396 may be present in the form of dangling bonds or other chargetrapping sites situated at an interface between dielectric layer 350 andpassivation layer 370, and/or at an interface between passivation layer370 and package material 380.

According to the implementation shown in FIG. 3A, shield plate 360 a isformed over dielectric 350 and is coupled to drain electrode 302. Shieldplate 360 a may be an electrically conductive plate, for example, suchas a metal plate, or a doped semiconductor plate. For instance, shieldplate 360 a may take the form of a P doped or N doped group III-V layeror plate having a doping concentration of at least approximately 10¹²charge/cm², such as a doping concentration of approximately 10¹³charge/cm². Alternatively, shield plate 360 a may be a substantiallyundoped semiconductor plate, or may be implemented as a resistive plate.

In implementations in which semiconductor or resistive shield plates areused, such shield plates may also act as additional field plates,examples of which are disclosed in U.S. patent application Ser. No.14/531,181, entitled “Group III-V Transistor with Semiconductor FieldPlate”, filed on Nov. 3, 2014 and claiming priority to provisional U.S.Patent Application No. 61/910,522, entitled “III-Nitride Transistor withSemiconductive Field Plate”, and filed on Dec. 2, 2013; as well as inU.S. patent application Ser. No. 11/322,923, entitled “III-Nitride PowerSemiconductor with a Field Relaxation Feature”, filed on Dec. 30, 2005,and published as U.S. Patent Application Publication Number 2006/0145189on Jul. 6, 2006. The disclosures in the above-referenced patentapplications are hereby incorporated fully by reference into the presentapplication.

As further shown in FIG. 3A, shield plate 360 a may extend at leastpartially over gate electrode 306 and field plate 316. Furthermore, insome implementations, shield plate may be situated over drain electrode302 and may extend over gate electrode 306, field plate 316, and atleast a portion of source electrode 304.

It is noted that shield plate 360 a should be configured such that itspresence does not adversely impact the performance of group III-V device300A. That is to say, although shield plate 360 a should be configuredto substantially shield device 2-DEG 346 from charge centers 394 and396, shield plate 360 a should not contribute to dielectric breakdown ofgroup III-V device 300A within its rated operating voltage range.Consequently, it is important that separation thickness 352 ofdielectric layer 350 be such that the breakdown voltage of separationthickness 352 is at least twice the rated voltage (or in certainapplications the time weighted average rated voltage in the application)of group III-V device 300A. For example, if the voltage rating of groupIII-V device 300A is approximately six hundred volts (600V), separationthickness 352 should be such that the dielectric breakdown of dielectriclayer 350 at separation thickness 352 is greater than or approximatelyequal to 1,200V.

It is further noted that although FIG. 3A shows separation thickness 352as spacing shield plate 360 a from field plate 316 overlying gateelectrode 306, the presence of field plate 316 is optional. Inimplementations in which field plate 316 is omitted, separationthickness 352 spaces shield plate 360 a from gate electrode 306 so as toelectrically isolate gate electrode 306 from shield plate 360 a.

Thus, according to the exemplary implementation shown in FIG. 3A, shieldplate 360 a is configured to substantially shield device 2-DEG 346 fromcharge centers 394 and 396 situated over shield plate 360 a. As aresult, the degradation in group III-V device performance due to chargetrapping in conventional device structures is reduced or substantiallyeliminated in group III-V device 300A due to the presence of shieldplate 360 a.

Continuing to FIG. 3B, FIG. 3B shows a cross-sectional view of exemplarygroup III-V device 300B including a floating shield plate configured toshield device 2-DEG 346 from charge centers 394 and 396, according toone implementation. It is noted that the features in FIG. 3B identifiedby reference numbers identical to those appearing in FIG. 3A correspondrespectively to those features, as described above, and may share any ofthe characteristics attributed to those corresponding features, above.

As shown in FIG. 3B, group III-V device 300B differs from group III-Vdevice 300A in FIG. 3A in that the implementation in FIG. 3B utilizesfloating shield plate 360 b, rather than shield plate 360 a, which, asshown in FIG. 3A, is coupled to drain electrode 302. By contrast,floating shield plate 360 b is spaced apart from and electricallyisolated from drain electrode 302 by dielectric layer 350.

Like group III-V device 300A, however, group III-V device 300B havingthe features shown in FIG. 3B may be implemented as a III-Nitride orother group III-V HEMT or FET or hybrid FET/HEMT device. Moreover, it isnoted that in addition to the features shown in FIG. 3B, group III-Vdevice 300B may further include some or all of the strain-absorbing,spacer, and capping layers described above by reference to FIG. 1. Forexample, group III-V device 300B may include an amorphous siliconnitride strain-absorbing layer between substrate 310 and transition body322, and/or one or more spacer to layers between device channel layer342 and device barrier layer 344, and/or a group III-V or insulatingcapping layer over device barrier layer 344, as discussed above.

Floating shield plate 360 b may be an electrically conductive plate, forexample, such as a metal plate, or a doped semiconductor plate. Forinstance, floating shield plate 360 b may take the form of a P doped orN doped group III-V layer or plate having a doping concentration of atleast approximately 10¹² charge/cm², such as a doping concentration ofapproximately 10¹³ charge/cm². Alternatively, floating shield plate 360b may be a substantially undoped semiconductor plate, or may beimplemented as a resistive plate. As shown in FIG. 3B, floating shieldplate 360 b is situated over drain electrode 302 and may extend at leastpartially over gate electrode 306 and field plate 316. Moreover, in someimplementations, floating shield plate 360 b may be situated over drainelectrode 302 and may extend over gate electrode 306, field plate 316,and at least a portion of source electrode 304.

Thus, according to the exemplary implementation shown in FIG. 3B,floating shield plate 360 b is configured to substantially shield device2-DEG 346 from charge centers 394 and 396 situated over floating shieldplate 360 b. As a result, the degradation in group III-V deviceperformance due to charge trapping in conventional device structures isreduced or substantially eliminated in group III-V device 300B due tothe presence of floating shield plate 360 b.

Moving to FIG. 4A and with continued reference to FIGS. 3A and 3B, FIG.4A shows a top view of an exemplary shield plate arrangement configuredto shield device 2-DEG 346 in FIG. 3A and/or FIG. 3B from charge centerssituated over device barrier layer 344, according to one implementation.FIG. 4A shows perspective lines 3A/3B-3A/3B depicting thecross-sectional views of structure 400A shown in FIGS. 3A and 3B. Inaddition, FIG. 4A shows drain fingers 402, source fingers 404, and gatefingers 406 corresponding respectively to drain electrode 302, sourceelectrode 304, and gate electrode 306, in FIGS. 3A and 3B. Also shown inFIG. 4A are shield plates 460 a/460 b, which may correspond to either ofshield plate 360 a or floating shield plate 360 b shown and describedwith reference to respective FIGS. 3A and 3B above.

It is noted that FIG. 4A is represented as though seen through packagematerial 380, passivation layer 370, and dielectric layer 350 in FIGS.3A and 3B. FIG. 4A shows drain runner 401 coupled to drain fingers 402,source runner 403 coupled to source fingers 404, and gate runner 405coupled to gate fingers 406. It is further noted that the presence offield plates corresponding to field plate 316, in FIGS. 3A and 3B areobscured by shield plates 460 a/460 b in the representation shown inFIG. 4A.

In FIG. 4A, shield plates 460 a/460 b extend over the length of eachdrain finger 402, i.e., as shown by the dashed lines in FIG. 4Aextending shield plates 460 a/460 b over the tips of drain fingers 402.However, in some implementations, it may be advantageous or desirable toterminate shield plates 460 a/460 b at some distance from the end of thedrain finger tips, as shown in FIG. 4A. It is noted that theimplementation shown in FIG. 4A utilizes drain finger terminationshaving an enhanced breakdown ellipsoidal design as disclosed in U.S.patent application Ser. No. 13/749,477, entitled “Transistor HavingIncreased Breakdown Voltage”, filed on Jan. 24, 2013, and published asU.S. Patent Application Publication Number 2013/0214330 on Aug. 22,2013. This patent application is hereby incorporated fully by referenceinto the present application.

According to the implementation shown in FIG. 4A, shield plates 460a/460 b are situated over drain fingers 402 and extend at leastpartially over gate fingers 406. However, in some implementations it maybe advantageous or desirable to have shield plates 460 a/460 b extendover drain fingers 402, gate fingers 406, and source fingers 404. Suchan implementation is shown in FIG. 4B.

Referring to FIG. 4B with continued reference to FIGS. 3A, 3B, and 4A,FIG. 4B shows a top view of structure 400B having an exemplary shieldplate arrangement configured to shield device 2-DEG 346 in FIG. 3Aand/or FIG. 3B from charge centers situated over device barrier layer344, according to another implementation. Like FIG. 4A, FIG. 4B isrepresented as though seen through package material 380, passivationlayer 370, and dielectric layer 350 in FIGS. 3A and 3B. FIG. 4B showsdrain runner 401 and gate runner 405, which are also shown in FIG. 4A.

In contrast to the implementation shown in FIG. 4A, FIG. 4B shows shieldplate 460 a/460 b extending over drain fingers 402, source fingers 404,and gate fingers 406 shown in FIG. 4A but not visible in FIG. 4B. Infurther contrast to FIG. 4A, according to the implementation shown inFIG. 4B, topside contact cannot be made to source runner 403, which iscovered by shield plate 460 a/460 b. Nevertheless, source runner 403 maybe electrically coupled to a conductive substrate of structure 400B(conductive substrate not shown in FIG. 4B) using substrate vias, or maybe electrically coupled to the backside of the die providing structure400B using through-wafer vias (vias also not shown in FIG. 4B).

As an alternative to electrically coupling source runner 403 to thesubstrate or backside of the die providing structure 400B usingthrough-wafer vias, source runner 403 shown in FIG. 4A can be eliminatedthrough use of source finger vias (i.e., vias located along the lengthof each source finger 404). In yet other implementations, it may beadvantageous or desirable to electrically couple gate fingers 406 to theback side of the die providing structure 400B using various via designs.

Moving to FIG. 5, FIG. 5 shows a cross-sectional view of exemplary groupIII-V device 500 including shield plate 560 configured to shield device2-DEG 546 from charge centers 594 and 596 above shield plate 560,according to one implementation. As shown in FIG. 5, group III-V device500 includes substrate 510, transition body 522 situated over substrate510, and buffer layer 524 situated over transition body 522. Inaddition, FIG. 5 shows device channel layer 542 situated over transitionbody 522, and device barrier layer 544 situated over device channellayer 542 to produce device 2-DEG 546. Also shown in FIG. 5 aredielectric layer 550, passivation layer 570, and package material 580,all situated above device barrier layer 544.

As further shown in FIG. 5, group III-V device 500 includes drainelectrode 502, source electrode 504, gate electrode 506, field plate 516overlying gate electrode 506, and shield plate 560. It is noted thatshield plate 560 may be a floating shield plate, as shown in FIG. 5. Inaddition, FIG. 5 shows separation thickness 556 of dielectric layer 550spacing shield plate 560 apart from each of gate electrode 506 and fieldplate 516. FIG. 5 also shows separation thickness 574 of dielectriclayer 550 spacing shield plate 560 apart from drain electrode 502 whenshield plate 560 is implemented as a floating shield plate.

Substrate 510, transition body 522, and buffer layer 524 correspond ingeneral to substrate 110, transition body 122, and buffer layer 124,respectively, in FIG. 1, and may share any of the characteristicsattributed to those corresponding features, above. In addition, devicechannel layer 542, device barrier layer 544, and device 2-DEG 546, inFIG. 5, correspond in general to device channel layer 142, devicebarrier layer 144, and device 2-DEG 146, respectively, in FIG. 1, andmay analogously share any of the characteristics attributed to thosecorresponding features, above.

Drain electrode 502, source electrode 504, and gate electrode 506, inFIG. 5, correspond in general to drain electrode 102, source electrode104, and gate electrode 106, respectively, in FIG. 1, and may share anyof the characteristics attributed to those corresponding features,above. Moreover, field plate 516, dielectric layer 550, passivationlayer 570, and package material 580, in FIG. 5, correspond in general tofield plate 316, passivation layer 370, dielectric layer 350, andpackage material 380, in FIGS. 3A and 3B, and may share any of thecharacteristics attributed to those corresponding features, above.

Group III-V device 500 having the features shown in FIG. 5 may beimplemented as a III-Nitride or other group III-V HEMT or FET or hybridFET/HEMT device. Moreover, it is noted that in addition to the featuresshown in FIG. 5, group III-V device 500 may further include some or allof the strain-absorbing, spacer, and capping layers described above byreference to FIG. 1. For example, group III-V device 500 may include anamorphous silicon nitride strain-absorbing layer between substrate 510and transition body 522, and/or one or more spacer layers between devicechannel layer 542 and device barrier layer 544, and/or a group III-V orinsulating capping layer over device barrier layer 544, as discussedabove.

According to the implementation shown in FIG. 5, device 2-DEG 546 isproduced by device barrier layer 544 and device channel layer 542 and issituated under shield plate 560. As a result, shield plate 560 issituated so as to substantially shield device 2-DEG 546 from chargetrapping resulting from the presence of charge centers 594 and 596 aboveshield plate 560.

As shown in FIG. 5, formation of dielectric layer 550, passivation layer570, and package material 580 over device barrier layer 544 can resultin the inadvertent formation of charge centers 594 and/or 596. Chargecenters 594 and/or 596 may be formed as point defects, such asimpurities, vacancies, and interstitials, for example, in the materialsused to provide dielectric layer 550, passivation layer 570, and packagematerial 580. Alternatively, or in addition, charge centers 594 and/or596 may be present in the form of dangling bonds or other chargetrapping sites situated at an interface between dielectric layer 550 andpassivation layer 570, and/or at an interface between passivation layer570 and package material 580.

According to the implementation shown in FIG. 5, shield plate 560 is afloating shield plate situated adjacent drain electrode 502, and betweengate electrode 506 and drain electrode 502. In addition, as shown inFIG. 5, in some implementations, shield plate 560 extends at leastpartially below field plate 516. Shield plate 560 may be an electricallyconductive plate, for example, such as a metal plate, or a dopedsemiconductor plate. For instance, shield plate 560 may take the form ofa P doped or N doped group III-V layer or plate having a dopingconcentration of at least approximately 10¹² charge/cm², such as adoping concentration of approximately 10¹³ charge/cm². Alternatively,shield plate 560 may be a substantially undoped semiconductor plate, ormay be implemented as a resistive plate.

It is noted that shield plate 560 should be configured such that itspresence does not adversely impact the performance of group III-V device500. That is to say, although shield plate 560 should be configured tosubstantially shield device 2-DEG 546 from charge centers 594 and 596,shield plate 560 should not contribute to dielectric breakdown of groupIII-V device 500 within its rated operating voltage range. Consequently,it is important that separation thickness 556 of dielectric layer 550 besuch that the breakdown voltage of separation thickness 556 is at leasttwice the rated voltage (or in certain applications the time averagerated voltage in the application) of group III-V device 500. Forexample, if the voltage rating of group III-V device 500 isapproximately 600V, separation thickness 556 should be such that thedielectric breakdown of dielectric layer 550 at separation thickness 556is greater than or approximately equal to 1,200V. As a specific example,separation thickness 556, as well as separation thickness 574 whenpresent, may be in a range from approximately 0.5 micrometer toapproximately 1.0 micrometer.

Thus, according to the exemplary implementation shown in FIG. 5, shieldplate 560 is configured to substantially shield device 2-DEG 546 fromcharge centers 594 and 596 situated over shield plate 560. As a result,the degradation in group III-V device performance due to charge trappingin conventional device structures is reduced or substantially eliminatedin group III-V device 500 due to the presence of shield plate 560.

Referring now to FIG. 6A, FIG. 6A shows a cross-sectional view ofexemplary group III-V device 600A including a shield plate configured toshield device 2-DEG 646 from charge centers 694 and 696 above device2-DEG 646, as well as a shield layer configured to shield device 2-DEG646 from charge centers 690 and 692 below device 2-DEG 646, according toone implementation. As shown in FIG. 6A, group III-V device 600Aincludes substrate 610, transition body 622 situated over substrate 610,and first buffer layer 624 situated over transition body 622. Inaddition, FIG. 6A shows device channel layer 642 situated overtransition body 622, and device barrier layer 644 situated over devicechannel layer 642 to produce device 2-DEG 646. Also shown in FIG. 6A areshield layer 630, and second buffer layer 628 situated between shieldlayer 630 and device channel layer 642. FIG. 6A further shows dielectriclayer 650, passivation layer 670, and package material 680, all situatedabove device barrier layer 644.

As also shown in FIG. 6A, group III-V device 600A includes drainelectrode 602, source electrode 604, gate electrode 606, field plate 616overlying gate electrode 606, and shield plate 660 a coupled to drainelectrode 602. It is noted that shield plate 660 a may be situatedbetween gate electrode 606 and drain electrode 602, as shown in FIG. 6A.In addition, FIG. 6A shows separation thickness 656 of dielectric layer650 spacing shield plate 660 a apart from each of gate electrode 606 andfield plate 616. Moreover, and as further shown in FIG. 6A, group III-Vdevice 600A may have charge centers 690 and/or 692 situated betweensubstrate 610 and device channel layer 642, as well as charge centers694 and/or 696 situated over device barrier layer 644.

Substrate 610, transition body 622, first buffer layer 624, and chargecenters 690 and 692 correspond in general to substrate 110, transitionbody 122, buffer layer 124, and charge centers 190 and 192,respectively, in FIG. 1, and may share any of the characteristicsattributed to those corresponding features, above. In addition, devicechannel layer 642, device barrier layer 644, and device 2-DEG 646, inFIG. 6A, correspond in general to device channel layer 142, devicebarrier layer 144, and device 2-DEG 146, respectively, in FIG. 1, andmay analogously share any of the characteristics attributed to thosecorresponding features, above. Moreover, shield layer 630 and secondbuffer layer 628, in FIG. 6A, correspond in general to respective shieldlayer 230 and second buffer layer 228, in FIG. 2, and may share any ofthe characteristics attributed to those corresponding features, above.

Drain electrode 602, source electrode 604, and gate electrode 606, inFIG. 6A, correspond in general to drain electrode 102, source electrode104, and gate electrode 106, respectively, in FIG. 1, and may share anyof the characteristics attributed to those corresponding features,above. In addition, field plate 616, dielectric layer 650, passivationlayer 670, and package material 680, in FIG. 6A, correspond in generalto field plate 316, passivation layer 370, dielectric layer 350, andpackage material 380, in FIGS. 3A and 3B, and may share any of thecharacteristics attributed to those corresponding features, above.Furthermore, charge centers 694 and 696 situated over device barrierlayer 644, in FIG. 6A correspond in general to respective charge centers594 and 596, in FIG. 5, and may share any of the characteristicsattributed to those corresponding features, above.

Group III-V device 600A having the features shown in FIG. 6A may beimplemented as a III-Nitride or other group III-V HEMT or FET or hybridFET/HEMT device. Moreover, it is noted that in addition to the featuresshown in FIG. 6A, group III-V device 600A may further include some orall of the strain-absorbing, spacer, and capping layers described aboveby reference to FIG. 1. For example, group III-V device 600A may includean amorphous silicon nitride strain-absorbing layer between substrate610 and transition body 622, and/or one or more spacer layers betweendevice channel layer 642 and device barrier layer 644, and/or a groupIII-V or insulating capping layer over device barrier layer 644, asdiscussed above.

According to the implementation shown in FIG. 6A, device 2-DEG 646 isproduced by device barrier layer 644 and device channel layer 642 and issituated over shield layer 630 and under shield plate 660 a. As aresult, shield layer 630 is situated so as to substantially shielddevice 2-DEG 646 from charge trapping resulting from the presence ofcharge centers 690 and 692 below device 2-DEG 646, while shield plate660 a is situated so as to substantially shield device 2-DEG 646 fromcharge trapping resulting from the presence of charge centers 694 and696 above device 2-DEG 646. That is to say, shield layer 630 isconfigured to substantially shield device 2-DEG 646 from charge centers690 and 692 situated between substrate 610 and shield layer 630, andshield plate 660 a is configured to substantially shield device 2-DEG646 from charge centers 694 and 696 situated over shield plate 660 a.

Shield plate 660 a may be an electrically conductive plate, for example,such as a metal plate, or a doped semiconductor plate. For instance,shield plate 660 a may take the form of a P doped or N doped group III-Vlayer or plate having a doping concentration of at least approximately10¹² charge/cm², such as a doping concentration of approximately 10¹³charge/cm². Alternatively, shield plate 660 a may be a substantiallyundoped semiconductor plate, or may be implemented as a resistive plate.

It is noted that shield plate 660 a should be configured such that itspresence does not adversely impact the performance of group III-V device600A. That is to say, although shield plate 660 a should be configuredto substantially shield device 2-DEG 646 from charge centers 694 and696, shield plate 660 a should not contribute to dielectric breakdown ofgroup III-V device 600A within its rated operating voltage range.Consequently, it is important that separation thickness 656 ofdielectric layer 650 be such that the breakdown voltage of separationthickness 656 is at least twice the rated voltage (or in certainapplications the time average rated voltage in the application) of groupIII-V device 600A. For example, if the voltage rating of group III-Vdevice 600A is approximately 600V, separation thickness 656 should besuch that the dielectric breakdown of dielectric layer 650 at separationthickness 656 is greater than or approximately equal to 1,200V. As aspecific example, separation thickness 656 may be in a range fromapproximately 0.5 micrometer to approximately 1.0 micrometer.

Thus, according to the exemplary implementation shown in FIG. 6A, shieldlayer 630 is configured to substantially shield device 2-DEG 646 fromcharge centers 690 and 692 situated between substrate 610 and shieldlayer 630, while shield plate 660 a is configured to substantiallyshield device 2-DEG 646 from charge centers 694 and 696 situated overshield plate 660 a. As a result, the degradation in group III-V deviceperformance due to charge trapping in conventional device structures isreduced or substantially eliminated in group III-V device 600A due tothe presence of shield layer 630 and shield plate 660 a.

Continuing to FIG. 6B, FIG. 6B shows a cross-sectional view of exemplarygroup III-V device 600B including shield layer 630 and a floating shieldplate, which together are configured to shield device 2-DEG 646 fromcharge centers 690, 692, 694 and 696, according to one implementation.It is noted that the features in FIG. 6B identified by reference numbersidentical to those appearing in FIG. 6A correspond respectively to thosefeatures, as described above, and may share any of the characteristicsattributed to those corresponding features, above.

As shown in FIG. 6B, group III-V device 600B differs from group III-Vdevice 600A in FIG. 6A in that the implementation in FIG. 6B utilizesfloating shield plate 660 b, rather than shield plate 660 a, which, asshown in FIG. 6A, is coupled to drain electrode 602. By contrast,floating shield plate 660 b is spaced apart from and electricallyisolated from drain electrode 602 by separation thickness 674 ofdielectric layer 650, which, for example, may be a separation thicknessin a range from approximately 0.5 micrometer to approximately 1.0micrometer.

Like group III-V device 600A, however, group III-V device 600B havingthe features shown in FIG. 6B may be implemented as a III-Nitride orother group III-V HEMT or FET or hybrid FET/HEMT device. Moreover, it isnoted that in addition to the features shown in FIG. 6B, group III-Vdevice 600B may further include some or all of the strain-absorbing,spacer, and capping layers described above by reference to FIG. 1. Forexample, group III-V device 600B may include an amorphous siliconnitride strain-absorbing layer between substrate 610 and transition body622, and/or one or more spacer layers between device channel layer 642and device barrier layer 644, and/or a group III-V or insulating cappinglayer over device barrier layer 644, as discussed above.

Floating shield plate 660 b may be an electrically conductive plate, forexample, such as a metal plate, or a doped semiconductor plate. Forinstance, floating shield plate 660 b may take the form of a P doped orN doped group III-V layer or plate having a doping concentration of atleast approximately 10¹² charge/cm², such as a doping concentration ofapproximately 10¹³ charge/cm². Alternatively, floating shield plate 660b may be a substantially undoped semiconductor plate, or may beimplemented as a resistive plate. According to the implementation shownin FIG. 6B, floating shield plate 660 b is situated between gateelectrode 606 and drain electrode 602. In addition, as shown in FIG. 6B,in some implementations, floating shield plate 660 b extends at leastpartially below field plate 616.

According to the exemplary implementation shown in FIG. 6B, shield layer630 is configured to substantially shield device 2-DEG 646 from chargecenters 690 and 692 situated between substrate 610 and shield layer 630,while floating shield plate 660 b is configured to substantially shielddevice 2-DEG 646 from charge centers 694 and 696 situated over floatingshield plate 660 b. As a result, the degradation in group III-V deviceperformance due to charge trapping in conventional device structures isreduced or substantially eliminated in group III-V device 600B due tothe presence of shield layer 630 and floating shield plate 660 b.

Thus, the present application discloses group III-V devices configuredsuch that the disadvantages associated with charge trapping inconventional device structures are reduced or substantially eliminated.According to various implementations of the present inventive concepts,one or more shield elements may be formed in the structure providing thegroup III-V device. In some implementations, such a shield element maybe configured to substantially shield the device 2-DEG from chargecenters situated over the device barrier layer. Moreover, in someimplementations, such a shielding element may take the form of a shieldplate disposed over the device 2-DEG.

From the above description it is manifest that various techniques can beused for implementing the concepts described in the present applicationwithout departing from the scope of those concepts. Moreover, while theconcepts have been described with specific reference to certainimplementations, a person of ordinary skill in the art would recognizethat changes can be made in form and detail without departing from thescope of those concepts. As such, the described implementations are tobe considered in all respects as illustrative and not restrictive. Itshould also be understood that the present application is not limited tothe particular implementations described herein, but manyrearrangements, modifications, and substitutions are possible withoutdeparting from the scope of the present disclosure.

1. A group III-V device comprising: a substrate; a transition bodysituated over said substrate; a device channel layer situated over saidtransition body, and a device barrier layer situated over said devicechannel layer thereby producing a device two-dimensional electron gas(2DEG); a drain electrode of said group III-V device coupled to saiddevice barrier layer; a shield plate coupled to said drain electrode,said shield plate configured to substantially shield said device 2DEGfrom charge centers situated over said device barrier layer.
 2. Thegroup III-V device of claim 1, wherein said shield plate is situatedover said drain electrode.
 3. The group III-V device of claim 1, whereinsaid shield plate comprises a metal plate.
 4. The group III-V device ofclaim 1, further comprising a gate electrode, wherein said shield plateextends at least partially over said gate electrode.
 5. The group III-Vdevice of claim 1, further comprising a gate electrode and a field plateoverlying said gate electrode, wherein said shield plate extends atleast partially over said field plate.
 6. The group III-V device ofclaim 1, wherein said shield plate comprises a doped group III-V layerhaving a doping concentration of at least approximately 10¹² charge/cm².7. The group III-V device of claim 1, further comprising a gateelectrode, wherein said shield plate is situated between said gateelectrode and said drain electrode.
 8. The group III-V device of claim1, wherein said shield plate comprises a semiconductor plate.
 9. Thegroup III-V device of claim 1, wherein said shield plate comprises aresistive plate.
 10. The group III-V device of claim 1, wherein saidgroup III-V device comprises a III-Nitride high electron mobilitytransistor (HEMT).
 11. A group III-V device comprising: a substrate; atransition body situated over said substrate; a device channel layersituated over said transition body, and a device barrier layer situatedover said device channel layer thereby producing a devicetwo-dimensional electron gas (2DEG); a drain electrode of said groupIII-V device coupled to said device barrier layer; a floating shieldplate being adjacent to said drain electrode, said floating shield plateconfigured to substantially shield said device 2DEG from charge centerssituated over said device barrier layer.
 12. The group III-V device ofclaim 11, further comprising a gate electrode, wherein said floatingshield plate is situated between said gate electrode and said drainelectrode.
 13. The group III-V device of claim 11, wherein said floatingshield plate comprises a metal plate.
 14. The group III-V device ofclaim 11, further comprising a gate electrode and a field plateoverlying said gate electrode, wherein said floating shield plateextends at least partially below said field plate.
 15. The group III-Vdevice of claim 11, wherein said floating shield plate comprises a dopedgroup III-V layer having a doping concentration of at leastapproximately 10¹² charge/cm².
 16. The group III-V device of claim 11,wherein said floating shield plate comprises a semiconductor plate. 17.The group III-V device of claim 11, wherein said floating shield platecomprises a resistive plate.
 18. The group III-V device of claim 11,wherein said floating shield plate is situated over said drainelectrode.
 19. The group III-V device of claim 11, further comprising agate electrode, wherein said floating shield plate extends at leastpartially over said gate electrode.
 20. The group III-V device of claim11, wherein said group III-V device comprises a III-Nitride highelectron mobility transistor (HEMT).